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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
December 2007
FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Features
Over 95% efficiency Internal power MOSFETs: High-side RDS(ON) = 31m Low-side RDS(ON) = 23m Integrated low-side Schottky diode Programmable frequency operation up to 750KHz Power-good signal Wide input range: 3.0V to 24V Output voltage range: 0.8V to 90%VIN Input under-voltage lockout (UVLO) Programmable over-current protection Under-voltage, over-voltage, and thermal protection Selectable light-load power-saving mode 5x6mm, 25-pin, 3-pad MLP
Description
The FAN2103 TinyBuckTM is an easy-to-use, cost- and space-efficient, synchronous buck solution. It enables designers to solve high-current requirements in a small area with minimal external components. External programming of clock frequency, current limit, and loop response allows for optimization and flexibility selecting output filter components and transient response. The summing current mode modulator uses lossless current sensing for current feedback and over-current, and includes voltage feedforward. Fairchild's advanced BiCMOS power process, combined with a thermally efficient MLP package, provides low-RDS(ON), internal MOSFETs, and the ability to dissipate high power in a small package. Under-voltage, thermal shutdown, and power-good are blanked at start-up, but protect the device from damage during fault conditions.
Applications
Thin and light Notebook PCs Graphics cards Battery-powered equipment Set-top box Point-of-load regulation
Related Application Notes
AN-5067 - PCB land pattern design and surface mount guidelines for MLP packages
Ordering Information
Part Number
FAN2103MPX FAN2103EMPX
Operating Temperature Range
-10C to 85C -40C to 85C
Package
25-Pin Molded Leadless Package (MLP) 5x6mm 25-Pin Molded Leadless Package (MLP) 5x6mm
Packing Method
Tape and Reel Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Typical Application Diagram
VIN CHF CIN
+5V RRAMP
C4
RAMP PGOOD EN VCC
P2 15
Q1
VIN BOOT
1
25 13 14 17 18 20 16 PWM MODULATOR P3 24 19
PGND PWM# FB
CBOOT
Q2 P1
SW
VOUT L COUT
RILIM RT
ILIM R(T) COMP
C2 C1 R2
AGND
R1 C3 R3
RBIAS
Figure 1. Typical Application
Block Diagram
Figure 2. Block Diagram
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Pin Configuration
Figure 3. MLP 5x6mm Pin Configuration (Bottom View)
Pin Definitions
Pin
P1, 6-12 P2, 2-5 P3, 21-23 1
Name
SW VIN PGND BOOT
Description
Switching Node. Power Input Voltage. Connect to the main input power source. Power Ground. Power return and Q2 source. High-side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC includes an internal synchronous bootstrap diode to recharge the capacitor on this pin to VCC when SW is LOW. Power-Good Flag. An open-drain output that pulls LOW when FB is outside a 10% range of the reference when EN is HIGH. PGOOD does not assert HIGH until the fault latch is enabled. ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the regulator after a latched fault condition. This input has an internal pull-up when the IC is functioning normally. When a latched fault occurs, EN is discharged by a current sink. Input Bias Supply for IC. The IC's logic and analog circuitry are powered from this pin. Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection. Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the default setting. Oscillator Frequency. A resistor (RT) from this pin to AGND sets the PWM switching frequency. Output Voltage Feedback. Connect through a resistor divider to the output voltage. Compensation. Error amplifier output. Connect the external compensation network between this pin and FB. Power Save Mode / Forced PWM. Connect to VCC to enable light-load, power-saving mode of operation. Connect to GND or leave open for fixed-frequency PWM mode. Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the ramp amplitude and provides voltage feedforward functionality.
13
PGOOD
14 15 16 17 18 19 20 24 25
EN VCC AGND ILIM R(T) FB COMP PWM# RAMP
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Parameter
VIN to PGND VCC to AGND BOOT to PGND BOOT to SW SW to PGND All other pins ESD AGND = PGND
Conditions
Min.
Max.
28 6 35
Unit
V V V V V V kV
-0.3 Transient (t < 20ns, F < 600KHz) Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 -5 -0.3 2.0 2.0
6.0 30 VCC+0.3
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC VIN TA TJ
Parameter
Bias Voltage Supply Voltage Ambient Temperature Junction Temperature
Conditions
VCC to AGND VIN to PGND FAN2103M FAN2103EM
Min.
4.5 3 -10 -40
Typ.
5.0
Max.
5.5 24 +85 +85 +125
Unit
V V C C C
Thermal Information
Symbol
TSTG TL TVP TI JC J-PCB PD Storage Temperature Lead Soldering Temperature, 10 Seconds Vapor Phase, 60 Seconds Infrared, 15 Seconds P1 (Q2) Thermal Resistance: Junction-to-Case P2 (Q1) P3 Thermal Resistance: Junction-to-Mounting Surface Power Dissipation, TA = 25C 4 7 4 35
(1)
Parameter
Min.
-65
Typ.
Max.
+150 +300 +215 +220
Unit
C C C C C/W C/W C/W C/W
2.8
(1)
W
Note: 1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 26. Actual results are dependent on mounting method and surface related to the design.
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Electrical Specifications
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Power Supplies
Conditions
SW = Open, FB = 0.7V, VCC = 5V, FSW = 600KHz Shutdown: EN = 0, VCC = 5V Power Saving Mode, VCC = 5V, FMIN Rising VCC Hysteresis
Min.
Typ.
Max.
Unit
8 7 2.2 4.1 4.3 300 31 23 255 540 300 600 50
12 10 4.5 4.5
mA A mA V mV
VCC Current
VCC UVLO Threshold Power Output Section N-Channel (Q1) RDS(ON) N-Channel (Q2) RDS(ON) Oscillator Frequency Minimum On-Time
(2)
VCC = 5V, 25C
35 25 345 660 65
m m KHz KHz ns V
RT = 50K RT = 24K 16VIN, 1.8VOUT, RT = 30K, RRAMP = 200K
Ramp Amplitude, pk-pk Minimum Off-Time Reference Reference Voltage (VFB) FAN2103M, FAN2103EM Error Amplifier DC Gain
(2) (2) (2)
0.53 100 150 806 805
ns mV mV PPM PPM dB MHz
FAN2103M, 25C FAN2103EM, 25C Temp. Coefficient (-10 to +85C) Temp. Coefficient (-40 to +85C)
794 795
800 800 50 70
80 VCC = 5V VCC = 5V, VCOMP = 2.2V VCC = 5V, VCOMP = 1.2V VFB = 0.8V, 25C RILIM open 25C, VCC = 5V Internal Temperature 2 Consecutive Clock Cycles 16 Consecutive Clock Cycles Measured at FB Pin Measured at FB Pin (VFB ~500mV) 110 68 12 0.4 1.5 0.8 -850 3.8 9
85 15 3.2 2.2 1.2 -650 5.0 10 160 30 115 73 250 250 120 78 -450 7.0 11
Gain Bandwidth Product Output Voltage (VCOMP)
V mA mA nA A A C C %VOUT %VOUT mV mV
Output Current, Sourcing Output Current, Sinking FB Bias Current Protection and Shutdown Current Limit ILIM Current Over-Temperature Shutdown Over-Temperature Hysteresis Over-Voltage Threshold Under-Voltage Shutdown Fault Discharge Threshold Fault Discharge Hysteresis
Note: 2. Specifications guaranteed by design and characterization; not production tested.
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Electrical Specifications (Continued)
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Soft-Start VOUT to Regulation (T0.8) Fault Enable/SSOK (T1.0) Control Functions EN Threshold, Rising EN Hysteresis EN Pull-up Resistance EN Discharge Current FB OK Drive Resistance PGOOD Threshold PGOOD Output Low PGOOD Output High PWM# Threshold PWM# Input Current VPWM# = 0.4V FB < VREF FB > VREF IOUT < 2mA VPGOOD = 5V
Conditions
Min.
Typ.
5.3 6.7 1.35 250 800
Max.
Unit
ms ms
Frequency = 600KHz
2.00
V mV K A
Auto-restart Mode -14 107
1 800 -11 110 -8 113 0.4 1 0.6 1.0 0.8 1.2
%VFB %VFB V A V A
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Typical Characteristics
1.010 1.005 V FB 1.000 0.995 0.990 -50 0 50 Temperature (oC) 100 150
1.20 1.10 I FB 1.00 0.90 0.80 -50 0 50 Temperature (oC) 100 150
Figure 4. Reference Voltage (VFB) vs. Temperature, Normalized
Figure 5. Reference Bias Current (IFB) vs. Temperature, Normalized
1500 1200 900 600 300 0 0 20 40 60 80 100 120 140 RT (K)
1.02 1.01 Frequency
Frequency (KHz)
600KHz
1.00
300KHz
0.99 0.98 -50 0 50 Temperature ( C)
o
100
150
Figure 6. Frequency vs. RT
Figure 7.
Frequency vs. Temperature, Normalized
1.60 1.40
I ILIM
1.04 1.02 1.00 0.98 0.96
RDS
1.20 1.00 0.80 0.60 -50 0 50 Temperature ( C)
o
Q1 ~0.32 %/ C Q2 ~0.35 %/ C
100 150
o
o
-50
0
50 Temperature ( C)
o
100
150
Figure 8. RDS vs. Temperature, Normalized (VCC = VGS = 5V)
Figure 9.
ILIM Current (IILIM) vs. Temperature, Normalized
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Application Circuit
Figure 10. Application Circuit: 1.8 VOUT, 500KHz
Typical Performance Characteristics
Typical operating characteristics using the circuit shown in Figure 10. VIN=16V, VCC=5V, unless otherwise specified.
100 95 90 Efficiency (%) 85 80 75 70 65 60 Effi8V (%) Effi12V (%) Effi_PSM_12V(%)
Loss (W)
Efficiency
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.00 Loss8V (W) Loss12V (W) Loss_PSM (W) Loss18V (W)
Power Loss
55 0.00
Power Saving Mode, 12VIN
0.50 1.00 1.50 Load Current (A) 2.00
Effi18V (%) 2.50 3.00
0.50
1.00
1.50 Load Current (A)
2.00
2.50
3.00
Figure 11.
1.828
1.8 VOUT Efficiency Over VIN vs. Load
Regulation Characteristic
Figure 12. 1.8 VOUT Dissipation Over VIN vs. Load
100 95
Efficiency
1.826
90
Efficiency (%)
Vo (V)
1.824
85 80 75 70 65 V IN =8V, 300KHz V IN =12V, 500Khz
1.822 Vo8V (V) 1.820 Vo12V (V) Vo18V (V) 1.818 0.00 0.50 1.00 1.50 2.00 Load Current (A) 2.50 3.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
Load Curr e nt (A)
Figure 13. 1.8 VOUT Regulation vs. Load
Figure 14. 3.3 VOUT Efficiency vs. Load (Circuit Values Changed)
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Typical Performance Characteristics (Continued)
Typical operating characteristics using the circuit shown in Figure 10. VIN=12V, VCC=5V, unless otherwise specified.
Figure 15. SW and VOUT Ripple, 3A Load
Figure 16. SW and VOUT Ripple, 0.5A Load
Figure 17. Transient Response, 1.5-3A Load (Circuit Values Changed)
Figure 18. Transient Response, 0.3-3A Load (Circuit Values Changed)
Figure 19.
Start-up, 3A Load
Figure 20.
Shutdown, 3A Load
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Circuit Description
Initialization
Once VCC exceeds the UVLO threshold and EN is HIGH, the IC checks for an open or shorted FB pin before releasing the internal soft-start ramp (SS). If R1 is open, the error amplifier output (COMP) is forced LOW and no pulses are generated. After the SS ramp times out (T1.0), an under-voltage latched fault occurs. If the parallel combination of R1 and RBIAS is 1K, the internal SS ramp is not released and the regulator does not start. Since VCC is used to drive the internal MOSFET gates, supply current is frequency and voltage dependent. Approximate VCC current (ICC) can be calculated using:
ICC(mA ) = 4.58 + [( VCC - 5 + 0.013) * (F - 128 )] 227
(1)
where frequency (F) is expressed in KHz. Setting the Output Voltage The output voltage of the regulator can be set from 0.8V to ~90% of VIN by an external resistor divider (R1 and RBIAS in Figure 1). The internal reference is 0.8V with 650nA, sourced from the FB pin to ensure that if the pin is open, the regulator does not start. The external resistor divider is calculated using:
- 0 .8 V V 0 .8 V = OUT + 650nA RBIAS R1
Soft-Start
Once SS has charged to 0.8V (T0.8), the output voltage is in regulation. Until SS reaches 1.0V (T1.0), the "Fault Latch" and power-saving mode operations are inhibited. To avoid skipping the soft-start cycle, it is necessary to apply VIN before VCC reaches its UVLO threshold. Soft-start time is a function of oscillator frequency.
EN 1.35V
2400 CLKs
(2)
Connect RBIAS between FB and AGND. To minimize noise on the FB node, the values of R1 and RBIAS should be selected to provide a minimum parallel impedance of 1K.
0.8V
FB
1.0V 0.8V Fault Latch Enable
Setting the Frequency
Oscillator frequency is determined by an external resistor, RT, connected between the R(T) pin and AGND:
F(KHz ) = 10 6 ( 65 * R T ) + 135
SS
3200 CLKs
(3)
where RT is expressed in K.
T0.8
4000 CLKs
T1.0
(10 6 / F) - 135 65 where frequency (F) is expressed in KHz. R T ( K ) =
(4)
Figure 21. Soft-Start Timing Diagram The regulator does not allow the low-side MOSFET to operate in full synchronous rectification mode until SS reaches 95% of VREF (~0.76V). This helps the regulator start against pre-biased outputs and ensures that inductor current does not "ratchet" up during the softstart cycle. VCC UVLO or toggling the EN pin discharges the SS and resets the IC.
The regulator does not start if RT is left open.
Calculating the Inductor Value
Typically the inductor is set for a ripple current (IL) of 10% to 35% of the maximum DC load. Regulators requiring fast transient response use a value on the high side of this range, while regulators that require very low output ripple and/or use high-ESR capacitors restrict allowable ripple current: IL = VOUT * (1 - D) L *F (5)
Bias Supply
The FAN2103 requires a 5V supply rail to bias the IC and provide gate-drive energy and controller power. Connect a >1.0f X5R or X7R decoupling capacitor between VCC and PGND. Whenever EN pin is pulled up to VCC, the 5V supply connected to VCC should be turned ON after VIN comes up. If the power supply is turned ON using EN pin with an external control after VCC and VIN come up, the VCC and VIN power sequencing is not relevant.
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
where F is the oscillator frequency, and L= VOUT * (1 - D) IL * F (6)
The selection of inductor influences the entry into power-saving mode. Consider minimum and maximum load conditions before inductor selection.
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Setting the Ramp Resistor Value
The internal ramp voltage excursion (VRAMP) during tON should be set to 0.6V. RRAMP is approximately: RRAMP(K ) = 18 x10 - 6 * VIN * F ( VIN - 1.8) * VOUT -2 (7)
Because the FAN2103 employs summing current-mode architecture, Type-2 compensation can be used for many applications. For applications that require wide loop bandwidth and/or use very low-ESR output capacitors, Type-3 compensation may be required. RRAMP provides feedforward compensation for changes in VIN. With a fixed RRAMP value, the modulator gain increases as VIN is reduced, which could make it difficult to compensate the loop. For designs with low input voltages (3V to 6.5V), it is recommended that separate RRAMP and the compensation component values are used as compared to designs with VIN between 6.5V and 24V.
where frequency (F) is expressed in KHz.
Setting the Current Limit
There are two levels of current limit thresholds in FAN2103. The first level of protection is through an internal default limit set at the factory to limit output current beyond normal usage levels. The second level of protection is a flexible one to be set externally by the user. Current limit protection is enabled whenever the lower of the two thresholds is reached. The FAN2103 uses its internal low-side MOSFET as the currentsensing element. The current-limit threshold voltage (VILIM) is compared to the voltage drop across the lowside MOSFET, sampled at the end of each PWM offtime/cycle. The internal default threshold (with ILIM open) is temperature compensated. The 10A current sourced from the ILIM pin can be used to establish a lower, temperature-dependent, current-limit threshold by connecting an external resistor (RILIM) to AGND:
Protection
The converter output is monitored and protected against extreme overload, short-circuit, over-voltage, and under-voltage conditions. An internal "Fault Latch" is set for any fault intended to shut down the IC. When the fault latch is set, the IC discharges VOUT by enhancing the low-side MOSFET until FB<0.25V. The MOSFET is not turned on again unless FB>0.5V. This behavior discharges the output without causing undershoot (negative output voltage).
RILIM(K) = 10.4 * K T * (IOUT -
IL ) + 142.5 2
0.25/0.5V
FAULT PWM GATE DRIVE PWM LATCH
(8)
FB
where: IOUT = desired current limit set point in Amps, KT = the normalized temperature coefficient of the low-side MOSFET (Q2) from Figure 8. After 16 consecutive, pulse-by-pulse, current-limit cycles, the fault latch is set and the regulator shuts down. Cycling VCC or EN restores operation after a normal soft-start cycle (refer to Auto-Restart section). The over-current protection fault latch is active during the soft-start cycle. Use a 1% resistor for RILIM.
Figure 23. Latched Fault Response
Under-Voltage Shutdown
If FB remains below the under-voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. This fault is prevented from setting the fault latch during soft-start.
Over-Voltage Protection / Shutdown
If FB exceeds 115% * VREF for two consecutive clock cycles, the fault latch is set and shutdown occurs. A shorted high-side MOSFET condition is detected when SW voltage exceeds ~0.7V while the low-side MOSFET is fully enhanced. The fault latch is set immediately upon detection. These two fault conditions are allowed to set the fault latch at any time, including during soft-start.
Loop Compensation
The loop is compensated using a feedback network around the error amplifier. Figure 22 shows a complete Type-3 compensation network. Type-2 compensation eliminates R3 and C3.
Auto-Restart
After a fault, EN is discharged with 1A to a 1.1V threshold before the 800K pull-up is restored. A new soft-start cycle begins when EN charges above 1.35V. Depending on the external circuit, the FAN2103 can be provisioned to remain latched-off or automatically restart after a fault. Figure 22. Compensation Network
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3 www.fairchildsemi.com 11
FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Table 1. Fault / Restart Provisioning EN pin Pull to GND VCC Open Cap to GND Controller / Restart State OFF (disabled) No restart - latched OFF Immediate restart after fault New soft-start cycle after: tDELAY (msec) = 3.9 * C(nf)
During power-saving mode, the output is regulated to a slightly higher value than its set point, since the current pulse is triggered when FB crosses VREF. The IC is prevented from switching in the audible band. If the FB pin has not dropped to VREF within 40s of the last pulse, the IC sinks current through the inductor to initiate a new cycle. Transition back to PWM mode is achieved when a load transient causes the output voltage to drop 1.5% below its regulation point.
1.85 1.84 1.83 1.82 1.81 1.8 1.79 1.78 0 0.25 0.5 0.75 1 1.25 1.5
PWM to PSM Transition PSM to PWM Transition
With EN left open, restart is immediate. If auto-restart is not desired, tie the EN pin to the VCC pin or drive it with a logic gate to keep the 1A current sink from discharging EN to 1.1V.
PSM to PWM PWM to PSM
Figure 25. Power-Saving Mode Regulation (Using Figure 10 Circuit) Power-saving mode operation can be disabled by connecting the PWM# pin to AGND, allowing only PWM operation. The PWM# pin has a 1A pull-down. If <0.6V is detected, power-saving mode operation is disabled. Figure 24. Fault Latch with Delayed Auto-Restart
PCB Layout Over-Temperature Protection
FAN2103 incorporates an over-temperature protection circuit that sets the fault latch when a die temperature of about 160C is reached. The IC is allowed to restart when the die temperature falls below 130C.
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when VOUT is out of regulation, as measured at the FB pin (thresholds are specified in the Electrical Specifications section). PGOOD does not assert HIGH until the fault latch is enabled (T1.0).
Power-Saving Mode
The FAN2103 maintains high efficiency at light load by changing to a discontinuous, constant peak current, power-saving mode (PSM). The transition to power-saving mode occurs when the load is Figure 26. Recommended PCB Layout
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
Physical Dimensions
2X
TOP VIEW
2X RECOMMENDED LAND PATTERN ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING PLANE
A) DIMENSIONS ARE IN MILLIMETERS. B) DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) DESIGN BASED ON JEDEC MO-220 VARIATION WJHC E) TERMINALS ARE SYMMETRICAL AROUND THE X & Y AXIS EXCEPT WHERE DEPOPULATED. F) DRAWING FILENAME: MKT-MLP25AREV2
BOTTOM VIEW
Figure 27. 5x6mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
www.fairchildsemi.com 13
FAN2103 -- TinyBuckTM 3A, 24V Input Integrated Synchronous Buck Regulator
(c) 2007 Fairchild Semiconductor Corporation FAN2103 Rev. 1.0.3
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